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HT62L256
Preliminary
Features
* Operation voltage: 2.7V~3.3V * Low power consumption: - Operating current: 20mA max. - Standby current: 2mA * High speed access time: 70ns * Input levels are LVTTL-compatible * Automatic power down when chip is deselected * Three state outputs * Fully static operation * Data retention supply voltage as low as 2.0V * Easy expansion with CS and OE options * 28-pin SOP/TSOP package
CMOS 32K8 Low Power SRAM
General Description
The HT62L256 is a 262,144-bit static random access memory organized into 32,768 words by 8 bits and operating from a low power range of 2.7V to 3.3V supply voltage. It is fabricated with high performance CMOS process that provides both high speed and low power feature with typical standby current of 2mA and maximum access time of 70ns. The HT62L256 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The HT62L256 supports the JEDEC standard 28-pin SOP and TSOP package.
Block Diagram
A0 A14 CS WE OE VDD VSS D0 D7 A d d re s s B u ffe rs X -D e c Y -D e c M e m o r y C e ll A r r a y ( 3 2 K 8 B its
R e a d /W r ite C o n tr o l L o g ic
S e n s e A m p lifie r O u tp u t B u ffe rs
Pin Assignment
A14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 VSS 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD WE A13 A8 A9 A11 OE A10 CS D7 D6 D5 D4 D3 O A1 A A A1 W VD A1 A1 A A A A A D 4 2 7 6 5 4 3 14 15 E E 1 9 8 3 1 28 A10 CS D7 D6 D5 D4 D3 VSS D2 D1 D0 A0 A1 A2
H T62L256 2 8 T S O P -A
H T62L256 2 8 S O P -A
Rev. 0.00 1 August 15, 2002
Preliminary
Pin Description
Pin Name A0~A14 WE OE CS D0~D7 VDD VSS I/O I I I I I/O 3/4 3/4 Address input pins Write enable signal pin, active LOW Output enable signal pin, active LOW Chip select signal pin, active LOW Data input and output signal pins Positive power supply Negative power supply, ground Description
HT62L256
Absolute Maximum Rating
VDD to VSS ........................................... -0.5V to +3.6V IN, IN/OUT Voltage to VSS ............. -0.5V to VDD+0.5V Power Consumption, PT .......................................0.7W Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Operating Temperature, TOP ......................0C to 70C Storage Temperature (Plastic), Tstg ... -55C to 125C
D.C. Characteristics
Symbol VDD VIL VIH ILI ILO VOL VOH IDD ISB1 ISB2 Parameter Operating Voltage Input Low Voltage Input High Voltage Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Current Standby Current Power Down Supply Current VIN=0 to VDD CS=VIH or OE=VIH, VOUT=0 to VDD VDD=Max, IOL=2mA VDD=Min, IOH=-1mA CS=VIH, IOUT=0mA CS=VIH, IOUT=0mA CS VDD - 0.2V, VIN0V Test Conditions 3/4 3/4 3/4
Ta=25C, VDD=3.0V10%, TOP=0C to 70C Min. 2.7 3/4 0.7VDD 3/4 3/4 3/4 VDD-0.3 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 2 Typ. 3.0 0 Max. 3.3 0.4 3/4 1 1 0.3 3/4 20 50 10 Unit V V V mA mA V V mA mA mA
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August 15, 2002
Preliminary
A.C. Characteristics
Symbol Read cycle tRC tAA tACS tAOE tCLZ* tOLZ* tCHZ* tOHZ* tOH Read Cycle Time Address Access Time Chip Selection Access Time Output Enable to Valid Outputs Chip Selection to Output in Low-Z Output Enabled to Output in Low-Z Chip Deselected to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change 70 3/4 3/4 3/4 10 5 3/4 3/4 10 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 70 70 35 3/4 3/4 25 25 3/4 Parameter Min. Typ.
HT62L256
Ta=25C, VDD=3.0V10% Max. Unit
ns ns ns ns ns ns ns ns ns
Write cycle tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW Note: Write Cycle Time Chip Selection to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High-Z Data Valid to End of Write Data Hold from End of Write Output Active from End of Write 70 60 0 60 50 0 3/4 30 0 5 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 20 3/4 3/4 3/4 ns ns ns ns ns ns ns ns ns ns
1. A write cycle occurs during the overlap of a low CS and a low WE 2. OE may be both high and low in a write cycle 3. tAS is specified from CS or WE, whichever occurs last 4. tWP is an overlap time of a low CS and a low WE 5. tWR, tDW and tDH are specified from CS or WE, whichever occurs first 6. tWHZ is specified by the time when DATA OUT is floating and not defined by the output level 7. When the I/O pins are in data output mode, they should not be forced with inverse signals
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Preliminary
A.C. Test Conditions Item Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level Output Load 0V to 3V 5ns 1.5V See figures below Conditions
HT62L256
+ 1 .5 V 1 .8 k W I/O 990W 100p. I/O
+ 1 .5 V 1 .8 k W
990W
5p.
* In c lu d in g s c o p e a n d jig
* In c lu d in g s c o p e a n d jig
O u tp u t lo a d
tC
LZ
, tO
O u tp u t lo a d fo r L Z , tC H Z , tW H Z a n d tO
W
Functional Description
Operation truth table CS H L L L Data retention characteristics Symbol VDR ICCDR tCDR tR Parameter VDD for Data Retention Data Retention Current Chip Disable Data Retention Time Operation Recovery Time Conditions CS VDD-0.2V VIN VDD-0.2V or VIN0.2V CS VDD-0.2V VIN VDD-0.2V or VIN0.2V See retention timing See retention timing Min. 2.0 3/4 0 tRC* OE X H L X WE X H H L Mode Standby Output Disable Read Write D0~D7 High-Z High-Z Dout Din Ta=-40C to 85C Max. 3.3 2 3/4 3/4 Unit V mA ns ns
Low VDD data retention timing
V
DD
3 .0 V V tC
DR DD
3 .0 V 2 .0 V tR V C SV
DD IH
CS V
IH
-0 .2 V
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Preliminary
Timing Diagrams
Read cycle 1 output enable controlled (1)
tR
C
HT62L256
A d d re s s tA
A
OE tA tO CS tA tC D
OUT LZ CS LZ OE
tO
H
tO tC
HZ HZ
D o n 't C a r e U nused
Read cycle 2 address controlled (1, 2, 4)
tR
C
A d d re s s tA
A
tO
H
tO
H
D
OUT
D o n 't C a r e U nused
Read cycle 3 chip select controlled (1, 3, 4)
A d d re s s tA tC D
OUT LZ CS
tC
HZ
D o n 't C a r e U nused
Note:
1. WE is high for read cycle 2. Device is continuously enabled, CS=VIL 3. Address is valid prior to or coincident with the CS transition low 4. OE=VIL 5. Transition is measured at 500mV from the steady state
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August 15, 2002
Preliminary
Write cycle 1 OE clock (1)
tW
C
HT62L256
A d d re s s tW
R
OE tC
W
CS
(5 ) tA
W
tW
P
WE
tA
S
tO D
OUT
HZ
(1 , 4 )
tD
W
tD
H
D
IN
D o n 't C a r e U nused
Write cycle 2 OE=VIL Fixed (1, 6)
tW
C
A d d re s s tC
W
tW
R
CS
(5 ) tA
W
tW
P
WE
tA
S
tO
H
tW D
OUT
HZ
tO
W
(7 )
(8 )
tD
W
tD
H
D
IN
D o n 't C a r e U nused
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August 15, 2002
Preliminary
Note: 1. WE must be high during all address transitions 2. A write occurs during the overlap (tWP) of a low CS and a low WE
HT62L256
3. tWR is measured from the earliest high going edge of CS or WE to the end of the write cycle 4. During this period, I/O pins are in the output state, so the input signals of opposite phase to the outputs should not be applied. 5. If the CS low transition occurs simultaneously or after with the WE low transition, the outputs remain in a high impedance state 6. OE is continuously low (OE=VIL) 7. DOUT is at the same phase as the write data of this write cycle 8. DOUT is the read data of the next address 9. If CS is low during this period, then the I/O pins are in the output state and the data input signals of the opposite phase to the outputs should not be applied 10. Transition is measured at 500mV from the steady state
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August 15, 2002
Preliminary
Package Information
28-pin SOP (330mil) outline dimensions
HT62L256
28 A
15 B
1
14
C C' G H D E .
a
Symbol A B C C D E F G H a
Dimensions in mil Min. 453 326 14 700 92 3/4 4 32 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 477 336 20 728 104 3/4 3/4 38 12 10
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August 15, 2002
Preliminary
28-pin TSOP (813.4) outline dimensions
HT62L256
H
D
1
28
E
q 0 .0 1 0 L D e ta il .
14 D
15
A2 A S e e D e ta il . L1 S S e a tin g P la n e b
y
e
A1
Symbol A A1 A2 b D HD E e L L1 q
Dimensions in mm Min. 3/4 0.08 0.95 3/4 11.70 13.20 7.90 3/4 3/4 3/4 0 Nom. 3/4 3/4 3/4 0.20 3/4 3/4 3/4 0.55 0.50 0.8 3/4 Max. 1.25 0.18 1.05 3/4 11.90 13.60 8.10 3/4 3/4 3/4 5
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August 15, 2002
Preliminary
HT62L256
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Sales Office) 11F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Semiconductor (Shanghai) Inc. 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor (Hong Kong) Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Holmate Semiconductor, Inc. 48531 Warm Springs Boulevard, Suite 413, Fremont, CA 94539 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright O 2002 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 0.00
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August 15, 2002

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